As semiconductor devices become more highly integrated, a design rule is reduced, and metal interconnection lines are multi-layered and miniaturized. In addition, as the associated metal interconnection line patterns are miniaturized, an aspect ratio of a contact or via hole increases. Therefore, it is difficult to completely fill the contact or via holes with tungsten (W).
In a conventional method, after forming a contact or via hole by etching an insulating layer, a barrier metal layer and plug are formed within the contact or via hole. However, as a result of the etching process, the size of the contact or via hole may be widened and the slopes thereof may be lowered. In addition, the aspect ratio thereof may increase. In this case, in a subsequent process for depositing a plug material, voids may occur within the plugs.
If there are voids in the plugs, metal interconnection line resistance increases. There is a problem in that operating speed of a semiconductor device may be lowered due to increase of RC delay due to the increased line resistance.